Tim Ryan

These are markers used in Verilog to force a type of FSM generation. These are needed if we can guarantee we generate the appropriate FSM types, but it may help...

For example, ``` fsm(one-hot) { ... } fsm(index/binary) { ... } fsm(gray) { ... } fsm(one-cold) { ... } ``` This could be extended to `sequence`s naturally.

Codegen is a useful feature in any language, and also an obvious footgun. 1. Extract macros into a language-level feature that allows templates to intersperse AST, FSM transitions, data, and...

Initial reset values are convenient but visibly separate from where the values are actually used. I prototyped a reset { } block that would assign initial values from variable declaration,...

The current "sequence" blocks are designed to convert sequential code into a state machine. This makes state machines easy to write, but hard to leverage their full expressive power. A...

Entity definitions

1

Borrowing another idea from VHDL (and Rust), it'd be nice to separate the entity definition from its logic/"architecture". ``` entity SpiMaster { in rst: bit, in clk: bit, in tx_trigger:...

Updates concurrent-hamt to work on Rust stable. 1.10 required because of stable compare-exchange functions.

This is an issue.

This is a slight rollback of the last rollback, but 0.10.18 fails with HEAD of node-addon-layer. This reverts the relevant parts for 0.10 in the short term until there's time...

Both will use JobObjects