Tim Ryan

Not to get ahead of myself, but I think this is how the code eventually will go: * `parser-haskell`, breaking out the LALRPOP code and AST parsing into a subcrate...

expr_explode doesn't take into account operator precedence

3

Right now it does a linear scan for the first operator, then splits an expression into two. Operator precedence would split at the highest-precedence operators first, then iterate on the...

Keywords "def" and "def mut"

1

This issue is for bikeshedding keywords. "def" is introduced as an analog for "wire" in Verilog, albeit more strictly typed (no latches should be inferred when using this). The term...

Testing and verification is the part of Verilog I'm weakest at. What should it look like if it were redesigned and implemented in Hoodlum?

This will allow the ethernet.hdl hack naming `__FSM_1` to be removed.

Currently, you can specify a unfixed width literal with a leading 0: ``` 115 => 115 0d115 => 115 0b1110011 => 115 0x73 => 115 ``` You can specify a...

In an on { } statement.