tanvi-shewale
tanvi-shewale
Where will I find this data?
I am not able to find these. Maybe the buffers are inserted at a later stage?
The die size is not a tight constraint right now. How do I increase the area?
I was able to increase the area and now the CTS phase is running fine. But it is getting stuck at step 40 where I get setup violations. I tried...
``` { "DESIGN_NAME": "decoder_logic", "VERILOG_FILES": "dir::src/*.v", "CLOCK_PERIOD": 20, "CLOCK_PORT": "clk", "CLOCK_NET": "ref::$CLOCK_PORT", "FP_PDN_VOFFSET": 7, "FP_PDN_HOFFSET": 7, "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", "FP_PDN_SKIPTRIM": true, "FP_SIZING": "absolute", "DIE_AREA": "0 0 1900 1600", "pdk::sky130*": { "FP_CORE_UTIL":...
So I have to increment my clock period at each instance?
I am getting this waring  Is this normal?
Is there a config setting to convert this into a macro so that I can use this multiple times as a part of other design?
I will check if it is working and update soon
Where can I find the spice files associated with the design? I wanted to integrate the design with an analog module and wanted the spice files