stnolting
stnolting
There are some (commercial) tools out there that have problems handling VHDL source files. Maybe it would be a nice feature to provide some kind of script that allows to...
@google provides some kind of framework with their [CFU-Playground](https://github.com/google/CFU-Playground) to add custom instructions to a RISC-V design. There is no real description of the interface, latency, et.c in their repo...
Most of the figures used in the documentation (mainly waveforms) are made with [WaveDrom](https://wavedrom.com/). It is possible to add those WaveDrom scripts right into the AsciiDoc source files of the...
Currently, there is no _explicit_ documentation of the (V)HDL source files beyond a lot of in-code comments. I have tried using DOXYGEN also for the HDL files - but that...
I wonder if there is an "official" way to check for `Z*` CPU extensions (like `Zicsr` or `Zifencei`)?! Executing a certain instruction (like `fence.i` from the `Zifencei` extensions) and checking...
@mikaelsky has suggested (in some issue I cannot find right now) to add a "`*.f`" file that list all required HDL files in their according compile order. This file could...
In a very custom version of the processor I am (_mis_)using the [Smcsrind](https://github.com/riscv/riscv-indirect-csr-access) ISA extension to add further CPU-local hardware accelerators. Even though those accelerators are not linked to the...
I would like to add some "identifier" to the processor's (AXI) stream ports. Something like a source ID and a destination ID so we can talk with several data sinks/sources...
Right now I am trying to port the core to a specific ASIC technology. Unfortunately, inferring RAM is ASIC world is not as easy as in FPGA world, so I...