Stelios Tzelepis

Depthwise 1D and 2D Resource strategy for io_stream

4

# Description - Related to #859 - [ ] Add a detailed description of the changes - Added `const` to the depth variable of the FIFOs between the Depthwise and...

FIFO depth optimizer for Vitis backend

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_FIFO depth_ optimizer for the Vitis backend using the built-in cosim FIFO profiling feature of Vitis HLS - Inserted the new optimizer to the Vitis backend flows - Implemented the...

Vitis Accelerator IP Flow

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Vitis Accelerator based on the IP Flow for Zynq devices (in contrast to #991 ), similar to the Vivado Accelerator. - Inherits from the Vitis backend - Generates the AXI...

Fix initiation interval of pooling and zeropadding layers on Vitis backend

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On the `Vitis` backend and `io_stream`, zeropadding and pooling layers don't reach `II=1` and are slower than for example the Conv layers ## Type of change - [x] Bug fix...

DSP packing Vivado backend

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[This report](https://docs.amd.com/v/u/en-US/wp486-deep-learning-int8) describes DSP packing for int8. I would like to extend it for quantization with fewer bits, increasing the speedup and reducing the DSP/LUT utilization even more. Things to...