Stefan Berndtsson

Sounds sensible. Should there be an implicit or explicit "end_of_instruction" step too, where the ucode can hook on exceptions/interrupts?

Yes, I think I'd prefer an explicit `end_sequence` there.

I think I'd rather see something like separate sequences. ``` static struct u_sequence add_sequence_reg_to_mem[] = { add_start, // Initialisation read_register, // Read register operand add_compute, // Do addition ea_begin_modify, //...

Things to consider regarding this and Bus/Address error. `ucyc` is a micro cycle, which is a 2c period of the 8MHz clock. With the EA sequence `nR nr`, this is...

How can a bus error be internally generated? Without a bus access, there shouldn't be a possibility for a bus error.

The next sentence there hints at it being identical in timing as well. > The bus cycle is aborted, and the processor ceases current processing and begins exception processing. I.e....

I was also thinking of the other exceptions here. A `TRAP` instruction should simply have the `TRAP` exception chain as part of its normal sequence (`TRAP` takes priority over trace...

My use of "identical" was because of the phrase "bus cycle is aborted". They're of course not really identical, since a bus error is triggered externally, and there could be...

Yes, I know about that one, and I had some thoughts of implementing it, but at the moment, I can't due to ostis being LGPL, and that code being GPL....