spatial-lang

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Updates for Plasticine

6

The following compiler changes should take effect when PIR gen is enabled: - [x] 1. Change switches to always be controllers (includes unit pipe insertion for conditions) [Priority 1] -...

dkoeplin

The first time I tried writing a 3D convolution where I MemReduce each slice of the cube into a 2D result, I wrote it this way: ``` val lineout =...

mattfel1

@raghup17 @mattfel1 @kelayamatoz This repository now has significantly more lines of C or Verilog than it does Scala, which made me look into what is taking up all those lines,...

dkoeplin

Improve FixPt and FltPt const type

2

Use more appropriate internal const type for FixPt and FltPt than BigDecimal.

rubenfiszel

What is going on here? I was looking at Stefan's lenet and there are strange things with c2_RF: There are 25 accesses to c2_RF, each parallelized by 4. In the...

mattfel1

compacting fifo is an expensive version of the legacy fifo used for lane-enabled accesses and when any lane can touch any bank. It probably makes sense to have the same...

mattfel1

There are some mods and divides in the critical path of compacting fifo operations. For now I squashed them into single cycle ops but we should probably tell the compiler...

mattfel1

Add stride to linebuf and shift reg

3

Example stride syntax: **LB:** val lb = LineBuffer[T](5, 28, s) **SR:** sr(r, *).shift2 ( lb(r, c::c+s) ) { y => y } An alternative syntax we discussed for SR was...

shadjis

scalameta upcoming features

1

For logging purposes, I was on the phone with @olafurpg from the scala-center and in the upcoming months those three fix should be solved in scalameta which should enable to...

rubenfiszel

Load/Store on part of struct

1

This is just a thing that would be nice to have: ``` @struct case class comp_acdc(index: UInt8, dc: UInt8, ac: UInt8 ) ... val ac_dram = DRAM[UInt8](64) ... val sram...

mattfel1