spatial-lang
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Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
Not sure whether this is a bug or feature. I was trying figure out why certain apps have unaligned loads/stores when tile size is a multiple of burst size. And...
``` val reg = Reg[Int] Reduce(reg)(0 by 1){i => ... }{ ... } ``` Case 1: The contents of `reg` after the loop is effectively unchanged. Is this the desired...
Building a Quicktest app for Xilinx ZCU102 Ultrascale+ board failed in the "make zcu-hw" step with the following error: [info] Compiling 117 Scala sources to /data/experiment/arch/spatial/spatial-lang/gen/Quicktest_zynq/target/scala-2.11/classes ... [error] /data/experiment/arch/spatial/spatial-lang/gen/Quicktest_zynq/chisel/IOModule.scala:48:18: not...
I added nodes and chisel backends for saturating ops by enclosing them in (like ``) and unbiased rounding by appending & (like `*&`) but I think there can be times...
I think we should support this kind of representation instead of/in addition to the current representation. I remember this is how MaxJ represented numbers. Right now, there is no way...
Cat API
Do we have an API for concatenate? Or is the only way to do it today is 1) Make a struct or pack the elements together 2) Cast them to...
Physically, we can do this. But shouldn't we throw an error since you should be using a HostIO and not an ArgOut? Currently it won't crash anywhere until chisel compilation
``` def FIR_Filter(args: Array[String]) { val input = StreamIn[Int](target.In) val output = StreamOut[Int](target.Out) val weights = DRAM[Int](32) val width = ArgIn[Int] val P = 16 (1,1,32) // Initialize width with...
We already made a lot of progress on getting this functionality through the connectDbgSig in MAGCore, we just need another kind of debug port that logs values to an sram...
Here is the operations that I noticed missing for FixPt so far: - [ ] log - [ ] exp - [ ] sqrt - [ ] acos - [...