Michael Büchler

The vertical synchronization is okay now, I can make out the 50 Hz sync pulses on the oscilloscope. * The pixel clock ("dclk") was wrong. A clock MUX selects the...

I had missed the part of `drivers/gpu/drm/rockchip/rockchip_drm_vop.c` that sets up the interlacing mode. But I can't get that to work properly. The way I see it, two different "line flag"...

With some debug output I had noticed that in `vop_crtc_atomic_enable()` there is a check for `vdisplay == 288` and that the actual value was twice (576). And also I had...

Maybe someone has the same W25Q256JV, bought it from the same shop, and can confirm or not confirm the problems I'm seeing?

The first indication would be the kernel message that I see on `dmesg` where it says "failed to read ear reg". If you also have this then my guess is...

Hi Johan, thanks for sharing your findings! If I interpret your document correctly then your solution was _not_ fitting the QSPI contents into the lower 16 MiB of the chip,...

> Using dd on the mtdblock device should be one way to test, yes! Just mind the partitioning that is described in the device tree (or in `/proc/mtd`). Up to...

> I am following the github discussion around the Renovate of the original HDL in LibreSDR and the incorporation in the LibreSDR Tezuka firmware. Sorry to hijack but I can't...

Hi! > Some roughly explanation how the 10 Mhz needs to work. The 10 Mhz signals is connected to a driver IC and then connected to the FPGA. The 7z020...

Hello Jaap, Thank you for clarifying some things. These devices are all new to me. I started looking into the [Ettus repository](https://github.com/EttusResearch/uhd) a bit. It's great to find all of...