Anna Slobodova
Anna Slobodova
In general SVAs are not synthesizable. On Nov 10, 2015, at 2:38 PM, David L. Rager [email protected] wrote: > Jared added support for parsing System Verilog Assertions (SVAs) in VL....
Thanks for the explanation., but it seems to me that the tests like that are at odds with generality of compliance tests. What if one does not implement virtual address...
How should I then interpret this sentence in user manual: "A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes for all memory accesses" if it is implicitly...