Steffen Jaeckel
Steffen Jaeckel
Both versions: 2.9.13+fcr Steps to reproduce: 1. On device 1 - "Create backup" 2. Transfer ceb files from device 1 to device 2 3. On device 2 - "Restore backup"...
# Description This PR contains the common (non board-specific) changes done while working on the port for Xilinx Versal. # Testing Ran `make check`. # Checklist - [ ] added...
# Description Complete port to Xilinx Versal with support for the AES-GCM, ECDSA, RSA, TRNG and SHA3-384 engines. ~The first part of this PR is handled in #5165~ **Edit**: This...
A placeholder issue to reference PR's that should be (at least partially) included in a potential 1.2.1 or 1.3.0
This adds support for setting a CRL in the SSL context.
### Checklist * [x] documentation is added or updated * [x] tests are added or updated ## Summary This adds support to decode most variations of PEM files. ### Changes...
### Checklist * [x] documentation is added or updated * [x] tests are added or updated ----- This adds support to create and build an amalgamated version of the library,...
Build system
I'm asking all of you contributors to your preferences when it comes to replace some of the makefiles with a "real buildsystem"^TM. I thought about one of the following: *...
* [x] documentation is added or updated * [x] tests are added or updated This PR adds support for the AES-NI instructions as discussed in e.g. #480 or #551
This modifies how the timing demo of RSA and ECC work. 1. it updates the timing output to be easier machine-readable. 1. it introduces reference-keys to measure the timing.