Zhaoyang You issues

Results 14 issues of


                                            Zhaoyang You

fix(NewCSR): when STCE in menvcfg is zero, STCE in henvcfg is read-only zero

feat(riscv64): Support RISC-V Zfa extension

* Support fli.s, fli.d, fminm.s, fminm.d, fmaxm.s, fmaxm.d * Support fround.s, fround.d, froundnx.s, froundnx.d, fcvtmod.w.d * Support fleq.s, fleq.d, fltq.s, fltq.d

fix(csr): fix intermediate storage reg for EX_II and EX_VI

Use one reg to store EX_II/EX_VI when output not fired.

fix(FuUnit, clkgate): use fu.io.in/out.fire control its clock gate enable signal

do not merge

Fix mhpmevent

fix(csr): fix interrupt code use xtopi.IID replace instread of xip & xie

* This PR fixes the interrupt code selection strategy. * The generation of the `xcause` interrupt number depends on the `default` interrupt priority, and the generation of the `xtopi` interrupt...

fix(csr, aia): add access siselect(vsiselect) in V mode

fix(Kconfig): use RV_AIA instead of RV_IMSIC

xstatus.vs=OFF, Permit Check

We need to check if xstatus.VS is OFF when executing vector inst or access vec CSR. Currently we perform vs checks on vector instructions without considering the H extension. we...

bug

fix(csr): set xstatus.VS dirty when a vector memory access instr has exception

* When the vstart of a vector memory access instruction is not 0, the xstatus.VS field is set to dirty.