sigmuha

True Dual Port Ram

6

Hi! I'm new to hdl-registers, and this looks like a very interesting project. :) One feature crucial feature for my projects are true dual port (tdp) rams. Are these supported...

**Describe the bug** When setting a note to be to the right of the starting point of a repeat loop, it gets inlined, as if it was an activity. **To...

Schematic viewer can't find library

1

**Describe the bug** When using the schematic viewer the following error is output: ``` 2025-04-22 09:17:43.670 [info] /home/asigmuh/stuff/mock_proj/src/top.vhd:6:9:error: cannot find resource library "sub_lib" library sub_lib; ``` **To Reproduce** Use the...

Change vscode work directory when changing projects.

2

**Is your feature request related to a problem? Please describe.** It would be nice if the workspace directory (the one used by vs-code) is switched to when selecting a project....

Schematic viewer: cannot configure on windows.

4

**Describe the bug** When configuring the schematic viewer for vhdl (GHDL + Yosys) and adding a path to start the oss-cad-suite environment, the `TerosHDL: Global` terminal doesn't produce any output,...

Merge vsg linter and formatter settings

16

**Is your feature request related to a problem? Please describe.** It is confusing to have to set the settings for vsg two times: One for the editor linter, and one...

Hi. Recently in a project, I was in need of using a lattice ice40 primitive: the SB_RAM40_4K. I can't seem to find a way to synthesize the design with the...

This issue is a feature request to have a version field for the package in the manifest `Bender.yml` file. A version field in the manifest would be useful for CI...