block-inclusivecache-sifive issues

If way0 has been used, new miss req may pick way0 to use even other ways were empty?

1

There is no lock way design? if no hit, no tagmatch, no bypass, it just picked victimway which is "random" generated by LFSR.

xiaochunsong92

has this project any unittest enviroment or verification enviroment ？

lenged

Update README.md

hcook

Control node should be duplicated per bank

In a distributed cache setting broadcasting the control signals out from the single control node to each bank is a physical design issue. For flush commands, there should be a...

jerryz123

remove objectmodule

This is needed for RC bumping after chipsalliance/rocket-chip#2967 get merged.

sequencer

What is "Block","Nest" and "BC_MSHR","C_MSHR"?

1

Hello,I'm reading the code,and don't understand why we should block and nest some request. and why there are two higher priority MSHR aloneside others?

ArcheyChen

L2 inclusive cache latency

I'm trying to figure out the clock cycle latency for the L2 inclusive cache - for a hit/miss etc. I can't seem to find it documented anywhere. Can anyone help?...

gdessouky