Ethan Sifferman

I ran this example through the big 4 to see what the outputs should be: ```systemverilog module tb; initial begin $info; $info("%b", 1); $warning; $warning("%b", 2); $error; $error("%b", 3); //...

As far as I can tell, all commercial tools support the SystemVerilog severity tasks __only when in SystemVerilog mode__. And I wasn't aware that Yosys had support. So I don't...

Actually, one issue I see is that Verilog ports don't support unpacked arrays. This makes me wonder if it would be better to flatten the ports, and assign to them...

I'm not currently sure how to include the filename, line number, and hierarchical scope, so I left it out. I can look into it later, but I may wait for...

Thanks for the code review! 1. I added `--exclude=SeverityTasks` 2. I've thought about the hierarchical scope more, and I'm not sure including it is important since it's not guaranteed the...

Just fixed the merge conflicts. Happy to make changes as needed!

> Scope and location information should be available via the Scoper module, the it's not super well documented, so I can take a stab at that if you'd like. Up...

Hello. I am managing the hardware implementation. Once we finish our optimizations and reorganizations, we will make the code available. We have several researchers at UCSC working on it, so...

@chili-chips-ba That is how sv-tests currently works for Yosys and Synlig: https://github.com/chipsalliance/sv-tests/pull/5139. The functionality can be easily extended to sv2v