sibeov

Enter GUI upon failed test?

7

Hi. Wondered if it is possible to enter GUI upon the first fail in a test. Is it possible to "catch" the fail someplace and rerun the previous test with...

Support for HDLs like VHDL, Verilog & SystemVerilog?

2

## Problem There is no Major for any HDL(Hardware Description Language)s as I see it. Like VHDL, Verilog and SystemVerilog. ## Solution Implement Major modes for HDLs? ## Alternatives Develop...

[QUESTION]: Automatic update files in project?

1

**Describe the bug** This is more of a question. Is it possible to access som API or similar to be able to automatically update or add files to the project....

**Is your feature request related to a problem? Please describe.** Unknown **Describe the solution you'd like** `vhdl_ls.toml` in the workspace folder instead of using a global `.vhdl_ls.toml` in the `$HOME`...

[FEATURE]: Failed to parse VUnit script indicator

1

**Is your feature request related to a problem? Please describe.** NA **Describe the solution you'd like** An indicator of sorts for when Teros is unable to parse a VUnit script...

[Question] How can I receive more than just four bytes? What I'm I doing wrong?

8

# Intro So! This is probably a user error on my part, but still. ## Problem This is is the source-code I'm working on. Simple transmit and receive. Yes! I...

Better error message for circular dependencies on import/include

1

### Description # Feature Request I would like to have better error messaging / handling of "Circular Dependency detected between and " or similar. This is where documents / packages...

[Suggestion]: Pytest equivalent "makefile" support for simulators?

1

# Intro So I'm currently trying to debug another issue and read the [Simulator Support](https://docs.cocotb.org/en/v2.0.1/simulator_support.html#) which more or less only refer to a makefile flow (if i'm not mistaken). Could...