shenghao

Hello, In general, ARM32 uses IR11 as the frame pointer register (i.e. FP) [1], but CompCert currently is using IR12 as FP. Considering the [following implementation](https://github.com/AbsInt/CompCert/blob/master/arm/Asm.v#L760), ```coq | Pallocframe sz...

Hi, The [register checking of assembler](https://github.com/solana-labs/rbpf/blob/main/src/assembler.rs#L234) should be consistent with that of [verifier](https://github.com/solana-labs/rbpf/blob/main/src/verifier.rs#L167) - dst should be [0,10] or [0,11] `!(0..16).contains(&dst)` -> `dst < 0 || dst > 11` or...

Hi, could we remove all [check_imm_shift](https://github.com/solana-labs/rbpf/blob/main/src/verifier.rs#L280) from the verifier, or do this checking during JIT's [emit_shift](https://github.com/solana-labs/rbpf/blob/main/src/jit.rs#L1166)? ```rust ebpf::LSH32_IMM => { check_imm_shift(&insn, insn_ptr, 32)?; }, ``` For the interpreter, the `wrapping_shl`...

Interperter CUs Computation questions

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Hello, I have two questions about CUs computation of the Solana interpreter, could someone please give me some suggestions? 1. The Solana interpreter says the CALL_REG spends an additional CU...

Hello, Could we merge some ALU and PQR instructions? As they have the same behaviour. If not, could someone please explain why Solana makes this choice? ```Rust //ALU32 and ALU64...