Jiuyang Liu

I think this Transform can reuse code from `firrtl.analyses.CircuitGraph`?

Here I have another question: If I wanna optimize the function of `def simplify(e: Expression, lhs: Literal, rhs: Expression) ` to `FoldAND`, `FoldOR`, `FoldXOR`, using a sequence of bits with...

for example: ``` val a = UInt(4.W) val b = a ^ 8.U(4.W) ``` `b` should be `Cat(!a(3),a(2),a(1),a(0))`

In this comment: https://github.com/freechipsproject/firrtl/issues/998#issue-401750878 `sOut_7` can not be optimized `sOut_7 = ! _T_730` is the same problem.

So what I wanna do is using `Cat` and `Not` to represent a `Expression` which has Constants. This can reduce the number of complex gates like `xor`. Although synthesis can...

Oh I got it.

`run_formal_checks` seems failed?

any update on this?

I believe the formal checks are false positives as jack said.

> Since ChiselEnum is a Chisel feature and not a firrtl feature, I think the essence of this annotation is providing a map from bit vector to string. > maybe...