Jiuyang Liu

Results 276 comments of Jiuyang Liu

Mark this issue depends on the new test framework to https://github.com/chipsalliance/rocket-chip/issues/2953

yeah we can document it firstly.

This should be merged a long time ago.

Joules or Voltus. Both of them are commercial tools.

I just pass by this issue for my CCC slide :) These comment copy and paste from my slide: constraint random is a easy Satisfiability Modulo Theory. We need an...

Yes, basically, it's a rename. I think the most important use case is directly test a verilog or other `RawModule` without wrapping it. And another case is that if user...

I'll work on this recently.

#156 experimentally solved this.

I have been thinking this: > Build a map between DUT top level IOs and the system verilog string names The future question might can be: how to map arbitrary...

Hello, @ducky64, if I wanna implement a `RawModule` tester without wrapper, what's the best way? I'm trying to port diplomatic module to tester2, But they are in `RawModule`.