Jiuyang Liu comments

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                                            Jiuyang Liu

Propose a PF/AF optional subset for long-vector implmentation

I’ll think about how to save/restore micro architectures status for t1 these days.

Propose a PF/AF optional subset for long-vector implmentation

Thought about it these days, do you think proposing an `pause` and `play` instruction to stall and unstall the vector unit is reasonable solution? Rather than save entire outstanding uArch...

How can I add the cache to rocket-chip?

This [PR](https://github.com/ucb-bar/chipyard/pull/128) may help you.

Model an Interconnect for Olympia

Hi, @knute-sifive FYI, The TileLink is updated to [1.9.3](https://sifive.cdn.prismic.io/sifive/928d6a82-77a9-4291-8b60-5e815429b1ab_tilelink_spec_1.9.3.pdf) I'm really curious about the methodology of designing SoC/interconnection performance model. We actually give a shot for Sparta this Q1, See...

Model an Interconnect for Olympia

Hi, Knute, > > We actually give a shot for Sparta this Q1 > > Fantastic! Be interesting to see what unfolds... We take these assumption: - Hierarchy between model...

Add support for RISCV V1.0 vector extension

FYI, https://github.com/chipsalliance/t1 is also another lane based implementation for RVV