Jiuyang Liu

The chipsalliance as upstream only accepts Apache, that the problem that rocketchip is unable to adopt the xiangshan's difftest. I'm drafting a RISC VIP based on Probe API and LTL,...

No, rocketchip will be split to smaller libraries, and user should handle the build flow on their own.

Spot my bug in chipsalliance/chisel#2924 https://github.com/chipsalliance/chisel/blob/440f01addeadd265fca2518c0a4df00b698e4603/src/main/scala/chisel3/util/experimental/decode/DecoderBundle.scala#L61 `asTypeOf` should never be LHS, otherwise it will create a wire and broken in when connection.... I'll vendor a chisel source for debugging, but...

Assign the Zb/Zk to @cyyself, I'll skip them in this PR by mask them off. After Chisel merging chipsalliance/chisel#3563 I'll bump Chisel version to 3.6.1 and 5.0.x and get this...

Since Zb/Zk is merged, I think it's OK to release a new version of 1.7. In the next dev-meeting, I'd like to discuss about mile stones of next releases: 1.8,...

I don't think there is any reason to bump major versions. 2.0 should be left for releasing breaking changes, for example "PvP version schemes", standalone "rocket", "tilelink" etc.

Every rtl change will break verification status . I still feel not good with major bumping for this reason. The CI in rocket chip is just sanity tests, and for...

You can version your own fork of rocket chip.

@SingularityKChen rebase to master plz

LGTM, but I'm not so familiar with printf API, @jackkoenig for review&approve.