scted

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Migen - Cat() simulation not matching verilog when Cat_object is sliced

Sounds like i'm not doing anything wrong in that I'm using 'Cat' as it is intended to be used. Doesn't look hopeful for {x, y}[a:b] Note: lines 20 and 21...

Migen - Cat() simulation not matching verilog when Cat_object is sliced

Love Migen BTW ... definitely delivers on the promise of making HDLs Pythonic ... hope this can get sorted out

Migen - Cat() simulation not matching verilog when Cat_object is sliced

( {} )[] not working either ... i'll try the other idea

Migen - Cat() simulation not matching verilog when Cat_object is sliced

i don't know about ghdl ... will look at it the workaround worked ... assigning to an intermediate signal and slicing that do we leave this open?

Migen - Cat() simulation not matching verilog when Cat_object is sliced

you can use Cat().l as the intermediate if you're careful ... 'l' doesn't make sense as an identifier if you are accessing both sides (l and r) of the wire...