Sébastien Bourdeauducq
Sébastien Bourdeauducq
Rebuild https://github.com/msys2/msys2-installer but with the ARTIQ packages included. Particularly useful in situations with air-gapped or GFW'd machines. Those typically are running Windows - so an offline Linux installer is less...
https://forum.m-labs.hk/d/646-sampler-reading-values-in-between-10-to-5v-when-input-is-0-5v/7
https://github.com/m-labs/artiq/issues/2174#issuecomment-1704391101
https://forum.m-labs.hk/d/622-eeprom-aliasing-when-using-drtio
``` warning: ./.Xil/Vivado-39-vulcan/realtime/tmp///parallel_timing.xdc:114: value not specified for "set_clock_groups -group" --------------------------------------------------------------------- Usage: set_clock_groups [-help] [-name ] [-physically_exclusive] [-logically_exclusive] [-asynchronous] [-allow_paths] [-group ]* [{>|>>} ] --------------------------------------------------------------------- warning: ./.Xil/Vivado-39-vulcan/realtime/tmp///parallel_timing.xdc:115: value not specified for...
* Example failure: https://nixbld.m-labs.hk/build/140594 * Triggered by the performance test run before it, e.g. with ``ARTIQ_ROOT=/home/sb/artiq/artiq/examples/kc705_nist_clock python -m unittest -v test_performance.TransferTest test_portability.HostVsDeviceCase`` * Seems more frequent since NixOS 22.11 (Python...
Currently, the dashboard displays every TTL or DDS channel available in the device database, with no way to select or reorder them. This is not nice on a large system...
The following code, with x a n-bit signal: `Cat(x+1, 1)` should produce a n+2 bit value (carry from the addition, plus 1 added by Cat). The simulator implements this behavior,...
Dual-port block RAMs in some FPGAs can have ports with different sizes. This feature cannot currently be used with Migen.