Sayantan Chakraborty

Implement missing AVX512 intrinsics

5

This PR, along with #1602, completes the AVX512 intrinsics. - [x] `AVX512F` - [x] `AVX512_BF16` - [x] `VEX` variants - [x] `AVX-VNNI` - [x] `AVX-VNNI-INT8` - [x] `AVX-NE-CONVERT` - [x]...

Implement AVX512_FP16

3

This PR adds the AVX512_FP16 intrinsics in Rust. These intrinsics will be behind the feature gate `#[feature(stdarch_x86_avx512_f16)]` (rust-lang/rust#127213). ### Progress: - [x] Set intrinsics - [ ] Arithmetic operations (Addition,...

Runtime detection of `xop` target-feature

1

This is an effort towards rust-lang/rust#127208. This Implements the runtime detection of `xop`.

Runtime detection for `AMX` target-features

2

This is an effort towards feature [`x86_amx_intrinsics`](https://github.com/rust-lang/rust/issues/126622). This implements the runtime detection for the 5 target-features for AMX. This depends on Rustc PR [#126639](https://github.com/rust-lang/rust/pull/126639), and should be merged together.

Add Runtime detection for SHA512, SM3 and SM4

2

This is an effort towards [#126624](https://github.com/rust-lang/rust/issues/126624). This adds run-time detection for these target features.

Add `evex512` target feature for AVX10

1

# Proposal Intel has introduced the new `AVX10.N-256` instruction set, which enables use of only the 256-bit instructions of the `avx512` set. LLVM uses the `evex512` feature flag to differentiate...

cpufeatures: requesting support for the newly added target features

3

Some new target features were added to Rust - [x] `sha512`, `sm3` and `sm4` (added in #1181) - [ ] `avxifma`, `avxvnni`, `avxvnniint8`, `avxvnniint16` and `avxneconvert` (rust-lang/rust#126617) - [ ]...

Change codegen of LLVM intrinsics to be name-based, and add llvm linkage support for `bf16(xN)`, `i1xN` and `x86amx`

50

This PR changes how LLVM intrinsics are codegen # Explanation of the changes ## Current procedure This is the same for all functions, LLVM intrinsics are _not_ treated specially -...

Simplify implementation of Rust intrinsics by using type parameters in the cache

8

The current implementation of intrinsics have a lot of duplication to handle different overloads of overloaded LLVM intrinsic. This PR uses the **base name and the type parameters** in the...

Add SIMD funnel shift and round-to-even intrinsics

13

This PR adds 3 new SIMD intrinsics - `simd_funnel_shl` - funnel shift left - `simd_funnel_shr` - funnel shift right - `simd_round_ties_even` (vector version of `round_ties_even_fN`) TODO: implement `simd_fsh{l,r}` in miri,...