Zihao Yu

fix instruction synchronization bug on a real RISC-V processor

1

@kaashoek Hi, I think the bug reported by #5 is still a problem. I am trying to explain in detail. This bug is related to instruction cache (ICache) in hardware....

emulator: bump verilator to support multi-threading simulation

2

**Related issue**: none **Type of change**: other enhancement **Impact**: no functional change **Development Phase**: implementation **Release Notes** Verilator supports multi-threading simulation starting with version 4.002. [Here](https://www.veripool.org/news/241-Verilator-Verilator-4-002-Released) is the news. I...

Fix compile error for chisel 6.0.0

2

**Related issue**: **Type of change**: bug report **Impact**: no functional change **Development Phase**: implementation **Release Notes** Fix compile error for chisel 6.0.0