salva-rczero

Hi @Fish-Git, As an exercise, more oriented to know Hercules better, than to provide a new facility (goal that I don't think is within my skills), I cloned the repository...

Thanks @Fish-Git, I made some progress: At opcode.c "e7xx" looks similar to "e6xx": ``` Line 1841: static INSTR_FUNC gen_opcode_e7xx[256][NUM_INSTR_TAB_PTRS]; Line 1897: #define execute_opcode_e7xx operation_exception Line 2818: /*E7*/ GENx370x390x900 ( ""...

Thanks you, @Fish-Git * 0C1 = operation exception (PIC 001). I'm sorry, I still think in JCL & Assembler. * I'm trying a STAK standalone core sample, following your instructions....

@Fish-Git Finally, I get the zVector facility enabled. Please check my updates at https://github.com/salva-rczero/hyperion-zvector. Thanks for your guidance and encouragement. Now I'll try to reach some vector instruction working as...

@Fish-Git I agree with the double implementation design. @mcisho > Is this your understanding too? Yes, this is how it was proposed, for byte size instructions it is not necessary...

@mcisho:   Can you explain to me why this line for LITTLE-ENDIAN? `int iv = ~(_v) & 0x1f; `

@mcisho While I appreciate your effort, I really don't understand the need for all these macros. Currently the working code only need: ``` #define VR_B(_v,_i) regs->vr[(_v)].B[(_i)] #define VR_H(_v,_i) regs->vr[(_v)].H[(_i)] #define...

@Peter-J-Jansen The first goal is to get it working, but yes, I have thought about using x86 SIMD for performance. In fact, a couple of Galois arithmetic instructions already use...

@mcisho Great! As soon as you make the branch and push the changes to `esa390.h` and `structs.h`, I'll start changes to `zvector.c` for endianness independence. On 64-127 bits, I would...

I've just created a pull request for the changes needed for vector instruccions (E7xx).