Rupert Swarbrick
Rupert Swarbrick
In the OpenTitan project, we use Verilator to (among other things) build a chip-level simulation. This is now reasonably large: it takes a minute or two to verilate and then,...
The main impetus for this came from trying to sort out an rv_dm test which was failing because of incorrect use of a clocking block (see "Remove use of HOST_CB...
The dout value here comes from pulp code in dmi_jtag_tap.sv (see the always_comb block that drives tdo_mux) and we'll almost get the BYPASS behaviour, but not quite. Since the correct...
This seems less complicated than the code that was there before, which had compiled the various DMI operations into their underlying JTAG writes without comments. Undoing this means I'm getting...
This is two commits, to allow us to merge the bug fix that found the dead primitive in the first place. The first commit is also in #22964, which should...
This PR has two commits. The first just makes some debug prints a bit more helpful. The second (the point of the PR) has the following commit message: This test...
The driver can sometimes decide to send special "dummy" DR or IR transactions. This is reasonable, but the end result is that we fall out of the Update-DR or Update-IR...
### Description The pulp code that we're vendoring for `rv_dm` contains some code that triggers Verilator warnings about address truncation. We're currently waiving the warning in `pulp_riscv_dbg.vlt`. When reviewing the...
I've spent a rather confusing couple of hours trying to diagnose behaviour that I'm seeing in OpenTitan. There, we have a [frontdoor agent](https://github.com/lowRISC/opentitan/blob/master/hw/dv/sv/jtag_dmi_agent/jtag_dmi_reg_frontdoor.sv) that does DMI transactions as follows: -...
I'm trying to debug a failure that's showing up in "rv_dm", a small wrapper around the `riscv-dbg` module in OpenTitan. The issue comes up when the JTAG clock is being...