Román Cárdenas Rodríguez

Hmm I see... the main issue with the volatile-register approach and the Rust ecosystem is that base addresses of peripherals are target-dependent. Therefore we need to deal with const generics...

I'm on vacation and I'll be traveling by the time of the meeting. I may have an Internet connection and be able to join, but I'm not 100% sure. @almindor...

As discussed in the embedded-group weekly meeting, we will use a raw pointer-based approach for RISC-V peripherals, mainly because of the different unsoundnesses of the `volatile-register` crate. However, I appreciate...

In case you are curious, I pushed a macro for generating CLINT peripherals and easing the access to `mtimecmp` registers for the different HARTS, you can take a look [here](https://github.com/romancardenas/riscv-peripheral/blob/main/src/macros.rs)...

Working example of [`riscv-peripheral`](https://github.com/romancardenas/riscv-peripheral)'s `PLIC`: https://github.com/greenlsi/hifive1/blob/rtc/examples/virq.rs

Related PR: #164

PWM is already implemented. I guess that this issue is already completed.

Same here! It is very difficult to work with large nested lists (compared to RStudio). If you could provide a mechanism to represent lists following RStudio's fashion it would be...

Now #815 implements this feature

I'm currently working on a PR for adding support to RISC-V targets over the SLIC. I hope to be done this week. Maybe I can add this change to the...