Rodrigo A. Melo

Well, we were testing with @eine and the context must be replaced by the use clauses, and it works. At least part of the fixup will be needed.

I was wrong. It works without changes returning `True` in `supports_vhdl_contexts`. I saw it in #684. @powARman did a good job and must be added as a co-author if this...

Trying the verilog user guide, I have this message: ``` xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning...

I have also the problem described in https://github.com/VUnit/vunit/issues/677#issuecomment-785206676 It finishes with the following change: ``` diff --git a/vunit/verilog/vunit_pkg.sv b/vunit/verilog/vunit_pkg.sv index 0498bf7..ed3875d 100644 --- a/vunit/verilog/vunit_pkg.sv +++ b/vunit/verilog/vunit_pkg.sv @@ -135,7 +135,7 @@...

With the following changes, the `examples/verilog/user_guide` works: ``` diff --git a/vunit/verilog/include/vunit_defines.svh b/vunit/verilog/include/vunit_defines.svh index 688bc7d..346b528 100644 --- a/vunit/verilog/include/vunit_defines.svh +++ b/vunit/verilog/include/vunit_defines.svh @@ -26,7 +26,7 @@ `define TEST_CASE_SETUP if (__runner__.is_test_case_setup()) `define TEST_CASE_CLEANUP if...

> Trying the verilog user guide, I have this message: > > ``` > xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use...

> I would consider this more as an informational message, not so much as a warning. The users should be able to see this message and decide on their own...

Hi @umarcor I perform the change to inherit Incisive from Xcelium, but I have pytest issues where I need help. I open https://github.com/rodrigomelo9/vunit/pull/1 to work on that.

@LarsAsplund @cmarqu @umarcor here is an update, to define possible next steps. In the current state of this PR: * `pytest tests/lint/` pass * `pytest tests/unit/` pass (also the added...

Ok @cmarqu let me know if you take a look. I will be working into a unified Cadence interface to be inherited by Incisive and Xcelium.