Add Cadence Xcelium support

[rodrigomelo9]

My attempt to provide support to Xcelium, based on previous Incisive support.

[rodrigomelo9]

Which one @cmarqu ? both of them? (I have no access to incisive).

[rodrigomelo9]

I broke something. In master, pytest tests/unit is ok, but in my branch, there are a lot of complaints about:

>       raise ArgumentError(action, message % conflict_string)
E       argparse.ArgumentError: argument --cdslib: conflicting option string: --cdslib

[rodrigomelo9]

To be able to launch a test, I removed Incisive from my local copy. I have complaints about vunit/tests/acceptance/artificial_out/xunit.xml (and effectively, artificial_out is not created).

[cmarqu]

Which one @cmarqu ? both of them? (I have no access to incisive).

Ah, the GitHub GUI is not really good here; I commented specifically on the line if simulator_is("activehdl", "xcelium"): in tests/acceptance/test_artificial.py.

[cmarqu]

I broke something. In master, pytest tests/unit is ok, but in my branch, there are a lot of complaints about:

>       raise ArgumentError(action, message % conflict_string)
E       argparse.ArgumentError: argument --cdslib: conflicting option string: --cdslib

You are adding the --cdslib option to the argument parser that it already knows about, from the Incisive support I think. Sounds like vunit assumes that all supported simulators have unique arguments (without collisions), which is not true here? You could rename the argument to e.g. --cdslib-xcelium as a workaround for now.

[rodrigomelo9]

@cmarqu taking into account that Xcelium is the newest, and Incisive could be deprecated sometime in the future, I defined the CLI arguments for both at xcelium.py. I put a note into incisive.py. What do you think?

[rodrigomelo9]

Which one @cmarqu ? both of them? (I have no access to incisive).

Ah, the GitHub GUI is not really good here; I commented specifically on the line if simulator_is("activehdl", "xcelium"): in tests/acceptance/test_artificial.py.

Solved.

[rodrigomelo9]

I applied two fixes in VHDL packages (based on https://github.com/VUnit/vunit/issues/325#issuecomment-907752061 and from #684) and now when I run under examples/vhdl/user_guide, I get:

<PATH>/vunit/examples/vhdl/user_guide$ python3 run.py
WARNING - /<PATH>/vunit/examples/vhdl/user_guide/tb_example_many.vhd: failed to find a primary design unit 'vunit_context' in library 'vunit_lib'
WARNING - /<PATH>/vunit/examples/vhdl/user_guide/tb_example.vhd: failed to find a primary design unit 'vunit_context' in library 'vunit_lib'
Compiling into vunit_lib: ../../../vunit/vhdl/string_ops/src/string_ops.vhd                        passed
Compiling into vunit_lib: ../../../vunit/vhdl/path/src/path.vhd                                    passed
Compiling into vunit_lib: ../../../vunit/vhdl/logging/src/print_pkg.vhd                            passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/types.vhd                             passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/codec_builder.vhd                     passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/codec_builder-2008p.vhd               passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/codec.vhd                             passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/codec-2008p.vhd                       passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/api/external_string_pkg.vhd           passed
  impure function read_char (
                          |
xmvhdl_p: *W,NORETN (/<PATH>/vunit/vunit/vhdl/data_types/src/api/external_string_pkg.vhd,35|26): No return statement in the body of function READ_CHAR.
  impure function get_ptr (
                        |
xmvhdl_p: *W,NORETN (/<PATH>/vunit/vunit/vhdl/data_types/src/api/external_string_pkg.vhd,42|24): No return statement in the body of function GET_PTR.
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/string_ptr_pkg.vhd                    passed
Compiling into vunit_lib: ../../../vunit/vhdl/logging/src/ansi_pkg.vhd                             passed
Compiling into vunit_lib: ../../../vunit/vhdl/logging/src/log_levels_pkg.vhd                       passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/string_ptr_pkg-body-2002p.vhd         passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/byte_vector_ptr_pkg.vhd               passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/api/external_integer_vector_pkg.vhd   passed
  impure function read_integer (
                             |
xmvhdl_p: *W,NORETN (/<PATH>/vunit/vunit/vhdl/data_types/src/api/external_integer_vector_pkg.vhd,35|29): No return statement in the body of function READ_INTEGER.
  impure function get_ptr (
                        |
xmvhdl_p: *W,NORETN (/<PATH>/vunit/vunit/vhdl/data_types/src/api/external_integer_vector_pkg.vhd,42|24): No return statement in the body of function GET_PTR.
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/integer_vector_ptr_pkg.vhd            passed
Compiling into vunit_lib: ../../../vunit/vhdl/logging/src/log_handler_pkg.vhd                      passed
Compiling into vunit_lib: ../../../vunit/vhdl/logging/src/print_pkg-body.vhd                       passed
Compiling into vunit_lib: ../../../vunit/vhdl/logging/src/logger_pkg.vhd                           passed
Compiling into vunit_lib: ../../../vunit/vhdl/dictionary/src/dictionary.vhd                        passed
Compiling into vunit_lib: ../../../vunit/vhdl/run/src/run_types.vhd                                passed
Compiling into vunit_lib: ../../../vunit/vhdl/logging/src/file_pkg.vhd                             passed
Compiling into vunit_lib: ../../../vunit/vhdl/logging/src/log_handler_pkg-body.vhd                 passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/integer_vector_ptr_pkg-body-2002p.vhd passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/integer_array_pkg.vhd                 passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/queue_pkg.vhd                         passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/string_ptr_pool_pkg.vhd               passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/queue_pkg-body.vhd                    passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/queue_pkg-2008p.vhd                   passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/integer_vector_ptr_pool_pkg.vhd       passed
Compiling into vunit_lib: ../../../vunit/vhdl/run/src/runner_pkg.vhd                               passed
Compiling into vunit_lib: ../../../vunit/vhdl/run/src/run_api.vhd                                  passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/queue_pool_pkg.vhd                    passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/integer_array_pkg-body.vhd            passed
Compiling into vunit_lib: ../../../vunit/vhdl/data_types/src/dict_pkg.vhd                          passed
Compiling into vunit_lib: ../../../vunit/vhdl/core/src/stop_pkg.vhd                                passed
Compiling into vunit_lib: ../../../vunit/vhdl/core/src/stop_body_2008p.vhd                         passed
Compiling into vunit_lib: ../../../vunit/vhdl/core/src/core_pkg.vhd                                passed
Compiling into vunit_lib: ../../../vunit/vhdl/run/src/run.vhd                                      passed
Compiling into vunit_lib: ../../../vunit/vhdl/logging/src/logger_pkg-body.vhd                      passed
Compiling into vunit_lib: ../../../vunit/vhdl/logging/src/log_levels_pkg-body.vhd                  passed
Compiling into vunit_lib: ../../../vunit/vhdl/logging/src/log_deprecated_pkg.vhd                   passed
Compiling into vunit_lib: ../../../vunit/vhdl/check/src/checker_pkg.vhd                            passed
Compiling into vunit_lib: ../../../vunit/vhdl/run/src/run_deprecated_pkg.vhd                       passed
Compiling into vunit_lib: ../../../vunit/vhdl/check/src/checker_pkg-body.vhd                       passed
Compiling into vunit_lib: ../../../vunit/vhdl/check/src/check_api.vhd                              passed
Compiling into vunit_lib: ../../../vunit/vhdl/check/src/check_deprecated_pkg.vhd                   passed
Compiling into vunit_lib: ../../../vunit/vhdl/check/src/check.vhd                                  passed
Compiling into lib:       tb_example_many.vhd                                                      failed
=== Command used: ===
/<TOOL>/19/19.09.002/tools.lnx86/bin/xrun -f /<PATH>/vunit/examples/vhdl/user_guide/vunit_out/xcelium/xrun_compile_vhdl_file_lib.args

=== Command output: ===
context vunit_lib.vunit_context;
                 |
xmvhdl_p: *E,SELLIB (/<PATH>/vunit/examples/vhdl/user_guide/tb_example_many.vhd,8|17): unit (VUNIT_CONTEXT) not found in library (VUNIT_LIB).
architecture tb of tb_example_many is
                                 |
xmvhdl_p: *E,ENNOFN (/<PATH>/vunit/examples/vhdl/user_guide/tb_example_many.vhd,14|33): Intermediate file for entity 'TB_EXAMPLE_MANY' could not be loaded, entity may require re-analysis.
xrun: *E,VHLERR: Error during parsing VHDL file (status 1), exiting.

Compile failed

Seems to be almost there :-D

[rodrigomelo9]

Well, we were testing with @eine and the context must be replaced by the use clauses, and it works. At least part of the fixup will be needed.

[rodrigomelo9]

I was wrong. It works without changes returning True in supports_vhdl_contexts. I saw it in #684. @powARman did a good job and must be added as a co-author if this PR reaches master.

[umarcor]

@rodrigomelo9 we picked one of the commits in #731. Can you please rebase?

[rodrigomelo9]

Trying the verilog user guide, I have this message:

xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.

Which disappears if I include the arg -disable_sem2009. I didn't found documentation about exactly what it means (which SV is using?). Seems ok to add this option? @cmarqu

[rodrigomelo9]

I have also the problem described in https://github.com/VUnit/vunit/issues/677#issuecomment-785206676

It finishes with the following change:

diff --git a/vunit/verilog/vunit_pkg.sv b/vunit/verilog/vunit_pkg.sv
index 0498bf7..ed3875d 100644
--- a/vunit/verilog/vunit_pkg.sv
+++ b/vunit/verilog/vunit_pkg.sv
@@ -135,7 +135,7 @@ class test_runner;
    function void cleanup();
       $fwrite(trace_fd, "test_suite_done\n");
       exit_without_errors = 1;
-      $stop(0);
+      $finish(0);
    endfunction
 
    function int loop();

But all the test pass:

Compile passed

Starting lib.tb_example_basic.all
Output file: /.../vunit/examples/verilog/user_guide/vunit_out/test_output/lib.tb_example_basic.all_58c2666aec61dbf9891244ed2152cee42a949488/output.txt
pass (P=1 S=0 F=0 T=4) lib.tb_example_basic.all (2.7 seconds)

Starting lib.tb_example.Test that a successful test case passes
Output file: /.../vunit/examples/verilog/user_guide/vunit_out/test_output/lib.tb_example.Test_that_a_successful_test_case_passes_2bdda5abfac164787ee41954d1c48bd036699331/output.txt
pass (P=2 S=0 F=0 T=4) lib.tb_example.Test that a successful test case passes (1.4 seconds)

Starting lib.tb_example.Test that a failing test case actually fails
Output file: /.../vunit/examples/verilog/user_guide/vunit_out/test_output/lib.tb_example.Test_that_a_failing_test_case_actually_fails_e0b95858e14bbfb897b8d111a43505ca7f742d28/output.txt
pass (P=3 S=0 F=0 T=4) lib.tb_example.Test that a failing test case actually fails (1.3 seconds)

Starting lib.tb_example.Test that a test case that takes too long time fails with a timeout
Output file: /...o/vunit/examples/verilog/user_guide/vunit_out/test_output/lib.tb_example.Test_that_a_test_case_that_takes_too_long_time_fails_with_a_timeout_f763c9dbbd826025101721b40758dfe8d596eff6/output.txt
pass (P=4 S=0 F=0 T=4) lib.tb_example.Test that a test case that takes too long time fails with a timeout (1.5 seconds)

==== Summary ==============================================================================================
pass lib.tb_example_basic.all                                                           (2.7 seconds)
pass lib.tb_example.Test that a successful test case passes                             (1.4 seconds)
pass lib.tb_example.Test that a failing test case actually fails                        (1.3 seconds)
pass lib.tb_example.Test that a test case that takes too long time fails with a timeout (1.5 seconds)
===========================================================================================================
pass 4 of 4
===========================================================================================================
Total time was 6.8 seconds
Elapsed time was 6.8 seconds
===========================================================================================================
All passed!

[rodrigomelo9]

With the following changes, the examples/verilog/user_guide works:

diff --git a/vunit/verilog/include/vunit_defines.svh b/vunit/verilog/include/vunit_defines.svh
index 688bc7d..346b528 100644
--- a/vunit/verilog/include/vunit_defines.svh
+++ b/vunit/verilog/include/vunit_defines.svh
@@ -26,7 +26,7 @@
 
 `define TEST_CASE_SETUP if (__runner__.is_test_case_setup())
 `define TEST_CASE_CLEANUP if (__runner__.is_test_case_cleanup())
-`define __ERROR_FUNC(msg) $error(msg)
+`define __ERROR_FUNC(msg) $display(msg); $finish(0)
 `define CREATE_ARG_STRING(arg, arg_str) \
    $swrite(arg_str, arg); \
    for (int i=0; i<arg_str.len(); i++) begin \
@@ -87,4 +87,4 @@
          `CREATE_ARG_STRING(variance, variance_str); \
              full_msg = {"CHECK_EQUAL_VARIANCE failed! Got ",`"got`", "=",  got_str, " expected ", expected_str, " +-", variance_str, ". ", msg}; \
              `__ERROR_FUNC(full_msg); \
-          end
\ No newline at end of file
+          end
diff --git a/vunit/verilog/vunit_pkg.sv b/vunit/verilog/vunit_pkg.sv
index 0498bf7..d5fc574 100644
--- a/vunit/verilog/vunit_pkg.sv
+++ b/vunit/verilog/vunit_pkg.sv
@@ -135,7 +135,7 @@ class test_runner;
    function void cleanup();
       $fwrite(trace_fd, "test_suite_done\n");
       exit_without_errors = 1;
-      $stop(0);
+      $finish(0);
    endfunction
 
    function int loop();
@@ -162,7 +162,7 @@ class test_runner;
                end
                else if (!found) begin
                   $error("Found no \"%s\" test case", test_cases_to_run[j]);
-                  $stop(1);
+                  $finish(1);
                   return 0;
                end
             end
@@ -218,7 +218,8 @@ class test_runner;
       fork : wait_or_timeout
          begin
             #(timeout_in_ns * 1ns);
-            $error("Timeout waiting finish after %.3f ns", timeout_in_ns);
+            $display("Timeout waiting finish after %.3f ns", timeout_in_ns);
+            $finish(0);            
             disable wait_or_timeout;
          end
          begin

Here the output after run the example:

==== Summary ==============================================================================================
pass lib.tb_example_basic.all                                                           (1.6 seconds)
pass lib.tb_example.Test that a successful test case passes                             (1.5 seconds)
fail lib.tb_example.Test that a failing test case actually fails                        (1.6 seconds)
fail lib.tb_example.Test that a test case that takes too long time fails with a timeout (1.5 seconds)
===========================================================================================================
pass 2 of 4
fail 2 of 4
===========================================================================================================
Total time was 6.2 seconds
Elapsed time was 6.2 seconds
===========================================================================================================
Some failed!

Basically, $stop and $error must be changed by $finish. I don't know @LarsAsplund how you deal with this kind of situations in other simulators. Based on a defined define? Preprocessing files? Let me know what we can do.

[rodrigomelo9]

Trying the verilog user guide, I have this message:

xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.

Which disappears if I include the arg -disable_sem2009. I didn't found documentation about exactly what it means (which SV is using?). Seems ok to add this option? @cmarqu

I found:

-disable_sem2009 Disable the default IEEE Standard 1800-2009 semantics for simulation. The Xcelium Simulator provides IEEE Standard 1800-2009 simulation semantics for SystemVerilog designs by default. Use this option on the command line to specify the Accelera Standard 3.1a, which has a different simulation cycle when compared to the IEEE Standard.

Is there something in Vunit to deal with that? Or must I provide a special option? Seems that not be used by default, but I don't know why the warning is there in Xcelium.

[cmarqu]

Trying the verilog user guide, I have this message:

xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.

Which disappears if I include the arg -disable_sem2009. I didn't found documentation about exactly what it means (which SV is using?). Seems ok to add this option? @cmarqu

I would consider this more as an informational message, not so much as a warning. The users should be able to see this message and decide on their own whether or not to set the option depending on their SV code.

[rodrigomelo9]

I would consider this more as an informational message, not so much as a warning. The users should be able to see this message and decide on their own whether or not to set the option depending on their SV code.

Ok, I agree.

[rodrigomelo9]

Hi @umarcor

I perform the change to inherit Incisive from Xcelium, but I have pytest issues where I need help. I open https://github.com/rodrigomelo9/vunit/pull/1 to work on that.

[rodrigomelo9]

@LarsAsplund @cmarqu @umarcor here is an update, to define possible next steps. In the current state of this PR:

• pytest tests/lint/ pass
• pytest tests/unit/ pass (also the added test_xcelium_interface.py)
• pytest tests/acceptance presents a lot of fails (log here)
• examples/vhdl/user_guide pass
• examples/verilog/user_guide pass after run python3 tools/xcelium_verilog_fixup.py
• I have another branch to inherit incisive from xcelium as suggested by @umarcor (https://github.com/rodrigomelo9/vunit/pull/1 where I need help because I have doubts about Vunit's internals)

[cmarqu]

Sorry, I can't test it for the next three weeks or so.

[rodrigomelo9]

Ok @cmarqu let me know if you take a look. I will be working into a unified Cadence interface to be inherited by Incisive and Xcelium.

[Hardolaf]

@rodrigomelo9 I'm wondering if you've had a chance to get this further down the path of working? I've rebased your branch on the latest master and fixed one decode issue in commits over on my branch here: https://github.com/Hardolaf/vunit/tree/add/xcelium-support

[rodrigomelo9]

Sorry, I did not further development on that. I'm not a VUnit user. It would be great if it reaches main (working, of course) :-D and I can try in a machine with access with Xcelium, but no more than that currently.

[VinieBerry]

I made an attempt to run VUnit with Xcelium 21.09 but still some issues.

I did the acceptance test and the current status is 28 failed, 13 passes and 8 skipped. I'm also running the examples.

Two issues happens quite often:

• Compilation issue in AlertLogPkg.vhd :

xmvhdl_p: *E,ALTYMM (/work/sesa595203/vunit/vunit/vhdl/osvvm/AlertLogPkg.vhd,3260|17): subprogram call or operator argument type mismatch 87[4.3.3.2] 93[4.3.2.2].
    if MetaMatch(L, R) then

• Simulation issue in codec.vhd

xmsim: *E,TRINDXC: index constraint violation.
          File: /work/sesa595203/vunit/vunit/vhdl/data_types/src/codec.vhd, line = 521, pos = 39
         Scope: @vunit_lib.codec_pkg:decode(STRING:STRING)

There is also a problem when calling VUnit in batch mode : the test ends but Xcelium does not exit (simulation stops still). I had to add the '-exit' argument to xrun call to fix this.

I will try in the coming weeks to work on that.

[VinieBerry]

I did a bit of progress since yesterday, I'm focusing on making the uart example working.

The implicit conversion between std_logic_vector and std_ulogic_vector seems not to be well supported by Xcelium. For instance at many places there is this kind of construct:

data := pop_std_ulogic_vector(request_msg); where data is declared as std_logic_vector

And it triggers this error:

xmvhdl_p: *E,EXPTYP (...): expecting an expression of type STD_LOGIC_VECTOR 87[8.4] 93[8.5].

To fix this, we can add an explicit cast but it is a bit painful and I'm not sure it is the best way to proceed (even this is what I did as a quick fix). This affects many files in the OSVVM and verification components libraries.

Another issue is the unconstrained type inside record, when the record type is used as a subprogram parameter. It is for instance the case in axi_stream_pkg.vhd at line 313. Based on Cadence support it is a known limitation...

[Hardolaf]

@VinieBerry I believe we can fix the OSVVM issues for some versions of Xcelium by checking to see if there is a Cadence provided version of OSVVM located at $XCELIUM_INSTALL_DIR/tools/inca/files/OSVVM and then defaulting to using that at least until there is a version of Xcelium which fully supports OSVVM (assuming OSVVM is correct; I'm very rusty on my VHDL as I haven't used it since 2018).

[VinieBerry]

Concerning the xmsim: *E,TRINDXC: index constraint violation error, it seems to appear only when a logging call is done with a mocked logger. Here is an example in the tb_logging_example.vhd:

-- Loggers can also be mocked
mock(my_logger);
failure(my_logger, "message");
check_only_log(my_logger, "message", failure);
unmock(my_logger);

0 fs - default                   -   TRACE - Verbose format
0 fs - default                   -   DEBUG - Verbose format
0 fs - default                   -    INFO - Verbose format
0 fs - default                   - WARNING - Verbose format
0 fs - default                   -   ERROR - Verbose format
0 fs - default                   - FAILURE - Verbose format
REPORT/NOTE (time 0 FS) from procedure @vunit_lib.logger_pkg:mock_log
Got mocked log item 
   time = 0 fs
   logger = logging_example:my_logger
   log_level = failure
   msg = message
   file_name:line_num = :0

xmsim: *E,TRINDXC: index constraint violation.
          File: /work/sesa595203/vunit/vunit/vhdl/data_types/src/codec.vhd, line = 521, pos = 39
         Scope: @vunit_lib.codec_pkg:decode(STRING:STRING)
          Time: 0 FS + 1

/work/sesa595203/vunit/vunit/vhdl/data_types/src/codec.vhd:521     variable ret_val : string(ret_range'range) := (others => NUL);
xcelium> exit

While:

-- Loggers can also be mocked
-- mock(my_logger);
failure(my_logger, "message");
check_only_log(my_logger, "message", failure);
-- unmock(my_logger);

0 fs - default                   -   TRACE - Verbose format
0 fs - default                   -   DEBUG - Verbose format
0 fs - default                   -    INFO - Verbose format
0 fs - default                   - WARNING - Verbose format
0 fs - default                   -   ERROR - Verbose format
0 fs - default                   - FAILURE - Verbose format
0 fs - logging_example:my_logger - FAILURE - message
REPORT/FAILURE (time 0 FS) from procedure @vunit_lib.core_pkg:core_failure
Stop simulation on log level failure
Report at 0 FS + 1
/work/sesa595203/vunit/vunit/vhdl/core/src/core_pkg.vhd:84       report msg severity failure;
xcelium> exit

This error happens 294 times in the acceptance test. I'm wondering if it is actually related to Xcelium simulator ? Does someone have already deal with this kind of issue ?

[VinieBerry]

The root cause of the xmsim: *E,TRINDXC: index constraint violation error is actually the 'ascending attribute returned value for strings when the length is zero. This occurs in the encode_array_header subprogram.

REPORT/NOTE (time 0 FS) from function @vunit_lib.codec_pkg:encode
Length is greater than 0
REPORT/NOTE (time 0 FS) from function @vunit_lib.codec_pkg:encode
Right = 7
REPORT/NOTE (time 0 FS) from function @vunit_lib.codec_pkg:encode
Left = 1
REPORT/NOTE (time 0 FS) from function @vunit_lib.codec_pkg:encode
Ascending = true
REPORT/NOTE (time 0 FS) from function @vunit_lib.codec_pkg:encode
Length is 0
REPORT/NOTE (time 0 FS) from function @vunit_lib.codec_pkg:encode
Right = 0
REPORT/NOTE (time 0 FS) from function @vunit_lib.codec_pkg:encode
Left = 1
REPORT/NOTE (time 0 FS) from function @vunit_lib.codec_pkg:encode
Ascending = false

I don't know why it seems to only happen with mocked logger (to be confirmed). For now my fix is to force to True the attribute value. Would it be possible to condition this depending on the simulator ?

[VinieBerry]

Another issue is the unconstrained type inside record, when the record type is used as a subprogram parameter. It is for instance the case in axi_stream_pkg.vhd at line 313. Based on Cadence support it is a known limitation...

Good news, I reported the issue to Cadence support and the answer is that it has been fixed and will be supported in a next release. This will be a great improvment since as of today we cannot compile all the VIP components (and therefore the associated testbenches).

[Hardolaf]

Doing more testing, I'm running into two issues:

1. The build times are slower compared to another simulator due to the repeated invocation of xrun during the compilation stage instead of running as a two or three stage xrun invocation. This appears to be primarily related to the startup time of the tool and the license check that occurs at startup.

2. When reinvoking using the same built libraries, the implementation can occasionally load the wrong testbench resulting in a false failure. I'm still trying to find the root cause of this issue.