Ryan Lee

Where do you think the "Last updated on:" should be (i.e. left, right, in between other elements)? As to the Sphinx default, I think the comments in `conf.py` explains this...

I was the one who originally set up the wiki instructions. When trying to open the GRIP project in Eclipse a few weeks ago, I found that Gradle had broken....

Documentation of major design decisions I am making (feel free to contest these in followup comments): * All signals and variables will be `std_logic_vector`s, with casts to `unsigned` and `signed`...

Technical debt to cleanup before finishing: - [ ] Everything labelled `TODO` in the code - [x] Array types are generated with the name `array_type_(width)`, so the signal renaming logic...

It turns out that more of the `id` related functions need updating, as the autogenerated `id`s need to be changed to be valid identifiers (without underscores at the beginning or...

Finally getting around to resuming development and copying over the `Mem` refactoring, but the requirement for placing signal declarations at the beginning for VHDL means that the actual memory dumping...

Unfortunately, I haven't had time to continue working on this, so I appreciate you stepping up to continue where I left off. I hope you'll be able to see this...

I added another example of the spurious warning, which also occurs when one imports two different files that state the same module name. This could occur in practice, for example,...

I would think that renaming the first module to a new name after importing would make the old name freely available, and that the second module (sharing the old name)...

I am going through the `write_verilog` file now to see how it is structured and what kinds of changes would be necessary. However, it also looks like `ghdl --synth` outputs...