Rafal Kapuscik

Could you specify the tool you're using and the exact error? I've created [this test](https://github.com/chipsalliance/UHDM-integration-tests/pull/686). It does fail in Yosys with Verilog frontend, but passes in UHDM frontend. I tested...

Could you provide more details on which tool are you using and with what options? I verified that UHDM plugin for yosys correctly parses this declaration - it is present...

Thanks for reporting, we will investigate this.

Thank you for reporting this. Can you confirm that this does not work in either frontend? If so, it would probably be a problem in Yosys itself and worth reporting...

Thanks for the test case. The error is indeed in Yosys itself - both frontends parse the loop and `$readmemh` call and generate the AST, but the simplify step in...

Thanks for reporting this. Generally errors with format like that (`[ERR:XXXX] ...`) come from Surelog, but I couldn't reproduce the one you reported. Can you share the file where you...

At this point Yosys doesn't support `break` statements, even with this plugin. We're currently looking into adding that.

> Is it ever the case that we would want to replace a child whose name is the same, but type is different? I don't think there is a case...

Thanks for working on this! Would you please add a simple [test](https://github.com/chipsalliance/yosys-f4pga-plugins/tree/main/systemverilog-plugin/tests) for those commands as well?

This is being worked on as part of https://github.com/antmicro/yosys-uhdm-plugin-integration/pull/913 - I'll try to split that PR to get some of the changes merged faster.