riscv-qemu

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RV64 mstatus/status: SXL and UXL are not correctly implemented

2

Hi ! The `misa` register correctly provides the value of `MXL`, but the `mstatus/sstatus` register do not provide a valid value for the `SXL` and `UXL` bits (which are always...

vsiles

Priv 1.10 should use *tval instead of *badaddr

2

From the Priv 1.10 preface: The 'mbadaddr' register has been subsumed by a more general 'mtval' register that can now capture bad instruction bits on an illegal instruction fault to...

msuozzo

Populating `mtval`/`stval` with instruction bytes on illegal instruction traps is an optional feature. We should add `RISCV_FEATURE_MTVAL_INST` to `target/riscv/cpu.h` and let cpus set this in their init functions so that...

michaeljclark

How to skip reset_vec execution before user program?

2

I run a bare metal RISC-V assembler program on QEMU. I use the following command: ``` qemu-system-riscv64 -M spike_v1.10 -cpu any -d in_asm -nographic -singlestep -bios program.bin ``` The simulation...

sergeysmolov

implement TSR, TW and TVM for privileged ISA v1.10

7

The `TVM` (Trap Virtual Memory) bit supports intercepting supervisor virtual-memory management operations. When `TVM=1`, attempts to read or write the `satp` CSR or execute the `SFENCE.VMA` instruction while executing in...

michaeljclark

misa.S indicates the machine supports S mode, and hence implements the s*CSRs, either returning the required values, or hard-coded to zero as specified. However, if S-mode is not implemented, s*...

michaeljclark

Currently the `csr_read_helper` and `csr_write_helper` TCG CSR helper function in `target/riscv/op_helper.c` are the only way to access CSR and they can generate illegal instruction exceptions. i.e. call longjump. We are...

michaeljclark

riscv linux-user should align stack to 16-byte boundary

1

> +static abi_ulong get_sigframe(struct target_sigaction *ka, > + CPURISCVState *regs, size_t framesize) > +{ > + abi_ulong sp = regs->gpr[xSP]; > + int onsigstack = on_sig_stack(sp); > + > +...

michaeljclark

When S-mode (misa.S) is not present, writes to mip/mip.SEIP/SSIP/STIP and mie/sie.SEIE/SSIE/STIE need to be masked. U-mode interrupts and the N-extension are not currently implemented, so these fields are already masked

michaeljclark

Support for RTC in virt machine

3

We are currently using `openrdate` (e.g., `rdate -s rdate.directadmin.com`) in Fedora stage4 to set clock once the system boots. The time goes out-of-sync, e.g. when you close your laptop lid...

davidlt