riscv-qemu
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Mask mie/mip fields depending on whether S mode is enabled (misa.S)
When S-mode (misa.S) is not present, writes to mip/mip.SEIP/SSIP/STIP and mie/sie.SEIE/SSIE/STIE need to be masked.
U-mode interrupts and the N-extension are not currently implemented, so these fields are already masked