riscv-qemu

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SiFive CLIC (Core Level Interrupt Controller) test-beta1

2

**_PLEASE DO NOT MERGE - QEMU CLIC BETA TEST V1_** - Implements draft clic-spec (20180728) - Implements non-vectored mode and vectored mode - Implements mode+level+priority configuration - Implements mode+level+priority preemption...

michaeljclark

I found that sometimes `tlb_fill` gets `size=0`, which I don't understand, and if `size=0`, PMP breaks on boundary addresses. https://github.com/riscv/riscv-qemu/blob/riscv-qemu-3.1/target/riscv/pmp.c#L187 Let's say PMP address range is 0x1000-0x1fff, ea will be...

dayeol

I found that the new PMP implementation skips any high-priority PMP rules. See code below, https://github.com/riscv/riscv-qemu/blob/riscv-qemu-3.1/target/riscv/pmp.c#L196 For example, if one of PMP entries matches, it must exit the loop and...

dayeol

Support loading binary files in addition to ELF files

2

The kernel and bootloader are not always available as ELF files, or directly executable. For example, the kernel might be included together with a device tree inside of an image....

lukasauer

Truncated register 16 in remote 'g' packet

12

Use a gdb (configured for RV64) to do remote debugging on a qemu-system-riscv32, it repots: "Truncated register 16 in remote 'g' packet". Is this a known issue? As a comparison,...

lbmeng

riscv: virt machine: multiple UARTs

8

Attach up to 16 serial devices, densely packed in the memory map and registered in the FDT. To ensure that BBL continues to find the default one, we register it...

nwf

Read/write of CSR registers via GDB doesn't work

1

A recent change in GDB revealed that the read/write of CSR registers via GDB doesn't work: https://sourceware.org/ml/gdb-patches/2018-07/msg00676.html Example output of a GDB client connected to GDB server of qemu-system-riscv32 or...

sebhub

When compiling a 32bit BBL and use it with the -bios parameter on the virt machine, I get an assert here: https://github.com/riscv/riscv-pk/blob/master/machine/minit.c#L78 If I comment this out and try to...

mickflemm

single float arith instructions don't produce NaN boxed output.

3

In translate.c, there is explicit code to NaN box the result of FLW. However, there is no equivalent code for any of the FP arithmetic instructions, add, sub, mul, div,...

jim-wilson

I have been experimenting with SiFive's FreeRTOS demo application: https://github.com/sifive/freedom-e-sdk/tree/FreeRTOS When I run the demo on QEMU without singlestep, the demo runs successfully: ~~~ qemu-system-riscv32 -machine sifive_e -nographic -kernel RISCV_HiFive1_GCC.elf...

arunthomas