About disassembler vsetvli

[joii2020]

When I enter 0xc5f957, it outputs vsetvli s2, a1, e16, m, tu, mu. (code)[https://github.com/riscv-software-src/riscv-isa-sim/blob/master/disasm/disasm.cc#L439] But I didn't find a description about the fourth parameter m in the rfc of rvv.

[ksco]

This is because 0xc5f957 is not a valid V instruction. Refer to riscv-v-spec Section 3.4.2, vlmul[2:0] = 0b100 is reserved.