riscv-coremark
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riscv-boom
Setup scripts and files needed to compile CoreMark on RISC-V
Hi, I'm interested in benchmarking the Shakti E-class core, which is a 32-bit core. I attempted to modify the files in riscv64/core_portme.mak, but encountered errors during the build process. I...
This PR fixes the bare-metal port plus adds some improvements: - Bumped the core `coremark` submodule - Do not force `ITERATIONS` in the build script - Allow providing the following...
Hi, I'm running multi-thread coremark on baremetal using pthread and get the following error. Does riscv toolchain support pthread? Or I miss some compilation options？Thanks！ Building Coremark Linux and Baremetal...
Hello, I want to run coremark for rv32i core in baremetal mode. I changed only the mak file, `build-coremark.sh` and Makefile. The changes are only the path definitions, the arch,...
Hi: under chipyard/sims/vcs folder, I compile the MediumBoomConfig boom instance, then try to run 100 iterations coremark. As the log below show, the CPU time spend 18 hours, however, the...
can anyone please help me running coremark benchmark on rocket-chip. how can I do it? and I'm still facing some errors.
Hi, I'm using this riscv-baremetal and find its default iterations alway equal to 40000. I have tried to change it to num 1 by cmd "./spike ./coremark.bare.riscv 0x0 0x0 0x66...
Hi, I 'm trying to run the coremark on the risc-v processor shakti c-class processor on FPGA. I used your code under this project. And below are the flags i...
Fixed: - Allowing Coremark score to be printed by disabling HAS_FLOAT, because syscalls.c does not support float printf. - Allowing user to define the bare-metal core frequency to reduce execution...
One day we will have `-mtune=boom`, for now `-mtune=sifive-7-series` is the right thing to use.
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Setup scripts and files needed to compile CoreMark on RISC-V