riscv-coremark
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riscv-boom
porting coremark issue
Hi, I 'm trying to run the coremark on the risc-v processor shakti c-class processor on FPGA. I used your code under this project. And below are the flags i used. -DFLAGS_STR=""-O2 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf -march=rv$(xlen)$(march) -w -static -nostartfiles -lgcc -T ./common/link.ld "" But when I run the program, it just quickly jumpt out and shows: 0x0000000080002594 in exit () at ./common/syscalls.c:49 49 asm volatile ( and the uart shows: Trap Cause: 5 encountered on PC:80002022. I'm not sure this is my compile problem or something else. It would be great if you could give some tipps. Thanks a lot. I'm looking forward to your reply.
Hi,
I am not an expert on this but I just stumbled across this issue and I think I have a similar problem. If I understand correctly, you are trying to run coremark bare metal on your FPGA. The problem is, that when you run the code bare metal, there is nothing in the processor to serve the syscalls. There is a riscv proxy kernel that could solve this problem, however, to my understanding it is not (easily) possible to run this on an FPGA. See my issue here: https://github.com/riscv/riscv-pk/issues/195
The bare metal version in this git is apparently designed to work with the spike simulator in combination with the proxy kernel (#3 )...
If you did manage to get this running on your FPGA, I would be happy, if you could tell me how you did it :-)
Hi, I managed to run the Benchmark on riscv-boom/ fpga-zynq zc706 with patch #6
The syscalls are served by syscalls.c :)
