Richard Meadows

Reopened after it was closed by an errant bors

According to the reference manual this delay is fixed at 10µs, and there's no dependance on the HCLK period. It is a good hypothesis though From DS12100, 10µs is the...

@ostenning Would you be able to take a look and see if the patch in https://github.com/stm32-rs/stm32h7xx-hal/pull/386 solves the problem?

There's nothing stopping you using this HAL with both cores already. However, we don't have any opinionated documentation about how you should organise your project (one crate or two, how...

Yes, these are significant changes! For now I say implement for Rev Y, then add `-rev_v` feature gates when someone has V silicon to test on.

Hi! I don't know of any development related to DCMI support so far, but contributions are very welcome! It's mostly that no one has gotten around to it, since the...

Previous comment from @astraw > I was thinking about a possible solution to the demo code: rather than putting it in examples/, we make sub-crates in this repo which would...

Is a simple solution just to make all the examples for the nucleo board? Then there's only one set to maintain. Other boards are less available (I have a custom...

+1 from me also. Printing via the [log crate](https://crates.io/crates/log) expects that users have a working log implementation (for example by copying one from the examples). I think that's reasonable.

The `GetClk` abstraction is generic enough to be moved into `embedded-hal`. But note `embedded-hal` asks for "two implementations of the trait(s) for different platforms", whilst the H7 crate is unique...