Rob Donnelly

:+1:

Verible looks to be doing the right thing here. SystemVerilog time literals can't have exponents. Here is the BNF from 1800-2017: Note that the BNF for `time_literal` does not include...

Verible is doing the right thing there. `0step` is not a valid SystemVerilog delay value. `1step` is the only valid delay value for the *step* delay unit. Here's the BNF...

### Update Overview I figured out a one line change that gets me most of the way there. However, the closing paren for the function ports list doesn't get put...

Another data point. DPI functions are formatted as desired. But non-DPI functions are not. Command: ``` ./bazelisk-linux-amd64 run //verilog/tools/formatter:verible-verilog-format -- $PWD/function.svh ``` Output ```SystemVerilog module some_module ( type_one port_one, type_two...

I'm getting closer to the desired result. I figured out how to get the closing paren on a new line. This piece of the code controls the formatting of the...

I've narrowed down this behavior to this section of the code: https://github.com/chipsalliance/verible/blob/8e8cc27d934f8f8bab13877cb457b47b35f0220c/verilog/formatting/token_annotator.cc#L500-L513 Here is a naïve fix that gives me the output I expected. ```diff diff --git a/verilog/formatting/token_annotator.cc b/verilog/formatting/token_annotator.cc index...

I see my confusion now. The two blocks were "either/or" instead of "and". This PR removes the confusion by eliminating one of the options.

@sakai135 please feel free to close if you'd like to resolve differently. Much thanks for your work on this project.

No solution yet but I suspect an issue with dvisvgm. I think the next step is reporting this to dvisvgm. I tried the original input using different versions of dvisvgm...