Romain Dolbeau

@enjoy-digital Yes I thought as much. Too bad, they seem to be nice cheap boards, but without LiteX what's the point ? :-) Intel has a tool to generate a...

@enjoy-digital I re-discovered the same issue; setting polling mode in Linux solved my ethernet problem as well - I can connect via SSH, do a NFS mount and so on...

No problem, it's an easy fix in the binutils tree. Now it's documented for those with similar issues :-)

@jim-wilson Unfortunately when using this repository, the scripts in `tools` points to an older version (https://github.com/riscv/riscv-bitmanip/blob/master/tools/checkout.sh still checkout `riscv-bitmanip` for riscv-binutils-gdb...) so the bug still appear to be present. So...

@JamesKenneyImperas @ben-marshall I think that currently @mjosaarinen code is for validation but does not yet include performance measurement. The benchmarks from this repo measure instructions count by default, but can...

@mohanson Yes the current binutils have a bug, see #93

Well theoretically yes for some definitions of SMP, but I was thinking more of the now-common cache-coherent SMP, where the implementation of A can play a role (i.e. atomic update...

> If it is not too much trouble, it would be interesting to see benchmark numbers from an Apple Silicon ARM machine. It would also be interesting to check on...

> I'm also interested in the SVE support for Raidz and Fletcher4. We have the AF64X hardware in the lab, and I plan to do the SVE support after done...

@slavonnet It should be possible to have a half-width (128 bits) version of the AVX2 code as VPMOVZXDQ is available in AVX; it would be near-identical to an hypothetical SSE4.1...