Raj Kumar Rampelli

Since the supported changes are not ready in VMR, below results are observed. Also, tried with temporary data set in XGQ driver manually in the clock_scaling's opcode response. **Reading clock...

Verified the PR on U2 board 

I have verified the PR using VMR.elf (local drop from Sandeep) which has clock scaling support. Able to read clock scaling default configurations during driver load time and dmesg will...

Verified the PR using latest qdma base-1 package taken from 2022.2_daily_latest builds. Flashable partitions running on FPGA Platform : xilinx_vck5000_gen4x8_qdma_base_1 SC Version : 4.4.35 Platform UUID : 9A3B9518-4E5A-B131-5FC0-D76AFF4C8991 Interface UUID...

Hi @rozumx could you please review this PR again. I have taken care of your review comments. Thank you.

All QDMA driver coverity fixes can be found at https://scan.coverity.com/projects/xilinx-xrt-5f9a8a18-9d52-4cb2-b2ac-2d8d1b59477f