Rafael do Nascimento Pereira

Results 14 comments of Rafael do Nascimento Pereira

> 1. Can you please shorten minimal.vim? The smallest possible config makes debugging easier. ```vim " plug - plugin manager call plug#begin('~/.config/nvim/plugged') Plug 'kaicataldo/material.vim' Plug 'vim-airline/vim-airline-themes' Plug 'myusuf3/numbers.vim' Plug 'neoclide/coc.nvim',...

I have the same issue. I am using the Vim 7.4.86 and the following plugins : 'gmarik/vundle' 'genutils' 'SelectBuf' 'VimExplorer' 'Color-Sampler-Pack' 'Tagbar' 'Syntastic' 'https://github.com/godlygeek/tabular.git' 'ctrlp.vim' 'myusuf3/numbers.vim' 'https://github.com/jistr/vim-nerdtree-tabs.git' 'https://github.com/scrooloose/nerdtree.git' 'https://github.com/tpope/vim-vividchalk.git' 'Valloric/YouCompleteMe'...

I just detected right now. It does not work with the "vividchalk" colorscheme. With other (i tested with 8 more) it worked since the start. Should i open a new...

@dycw thanks for you reply, now it is clear. 👍 :slightly_smiling_face:

@ttonnellier thanks, I got the basics working. ![image](https://user-images.githubusercontent.com/1737706/151263776-035a27b9-d6db-40da-8faa-a3c669986684.png)

I suppose the [base_builder.py](https://github.com/suoto/hdl_checker/blob/master/hdl_checker/builders/base_builder.py) and [ghdl.py](https://github.com/suoto/hdl_checker/blob/master/hdl_checker/builders/ghdl.py) would be a good starting point, would they?

I add some initial code to detect verilator and its version. So far I was not successful, mainly due to my poor python skills. Do you have any suggestions for...

Do you suggest/have, beside the corresponding projects documentation, any tutorial for docker and tox? I am not acquainted with both, specially the latter.

Thanks for the tips, I am making some progress here. I forked the project and I am working on a branch called `verilator`.

I was able to get a basic parsing for verilator to work, but the results are not shown on neovim. The `_mapLibrary` and `_creatyLibrary` methods just have a `pass`, Verilog...