YenFuChen

I implemented [T2C](https://github.com/qwe661234/rv32emu/tree/background_T2C) with a background thread and a compilation wait queue. Once the target block exceeds the condition for launching T2C, it is added to the compilation wait queue....

In the implementation of `jit-arm64.[ch]`, our objective is to harmonize the API of `ARM64` with that of `X64`. This allows us to efficiently reuse the existing JIT template from X64...

After investigating the difference in dynamic instruction count between `riscv32-unknown-elf-gcc` and x64 native `gcc`, we observed that the significant difference is caused by the powerful Intel instruction `rep movsb`. This...

I have successfully built a simple sum program using the LLVM-C API in two ways. The first approach involves building LLVM IR through the API and utilizing `LLVMLinkInMCJIT`. To adopt...

I have implemented a tier-2 just-in-time compiler through two approaches: 1. RISC-V INSN IR -> C code -> clang 2. RISC-V INSN IR -> LLVM IR -> LLVM JIT Based...

There are several optimization strategies mentioned in [`Optimizing Performance Using Dynamic Code Generation`](https://mediatum.ub.tum.de/doc/1614897/1614897.pdf) that we can apply to rv32emu. ## For tier-1 JIT compiler ### Function Representation A function is...

Next, we will make several further improvements: ## Tier-1 JIT compiler * Implement register allocation on generated machine code . * Finding an approach to detect function. ## Tier-2 JIT...

After implemented register allocation for T1C and adding some LLVM opimization passes mentioned in [Optimizing Performance Using Dynamic Code Generation](https://mediatum.ub.tum.de/doc/1614897/1614897.pdf) for T2C, The performance of rv32emu with a tiered framework(T1C...

After improving indirect jump for T1C, The performance of rv32emu with a tiered framework(T1C & T2C) is very close to that of QEMU and even surpasses in some cases. *...

Here, we also compare the hardware events: * iTLB-load-misses * cache-misses * page-faults between QEMU and rv32emu. Based on the analysis below, fast interpreter & T1C use less memory to...