Lucian Petrica

Thanks @PedrooHR for reporting this. I was able to replicate this issue on our end.

Appears that #134 improves soft reset functionality but is not a complete fix.

your `deinit()` issues are probably a race condition with XRT destruction. Since the ACCL destructor uses XRT to access the CCLO and clean it up, it must always run before...

Hi @Mellich Could you clarify this: "It occurs using the UDP and TCP stack." I can see a mechanism whereby backpressure from the RX pipeline causes the UDP stack to...

Traced this problem back to ACCL applying backpressure into the POE which causes packet loss with UDP and with TCP if RX bypass is enabled. The current work-around is to...

@Mellich what shell are you targeting? I haven't checked that script for a long time and TBH i don't remember which shell it was written for. The path to the...

From [Vitis documentation](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_1/ug1393-vitis-application-acceleration.pdf): The READ_LATENCY [...] attribute [...] sets the number of pipeline stages between memories cascaded in depth [...] A good rule of thumb is to pick a read...