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                                            Peter

build failure for smunaut/libsigrok

i have this problem too

i am use the previous verions of Verilog2001.g4 https://gitlab.com/quantr/toolchain/verilog-compiler/-/blob/main/src/main/java/hk/quantr/verilogcompiler/antlr/Verilog2001.g4 , my pom.xml is in https://gitlab.com/quantr/toolchain/verilog-compiler I tried 4.9.2 and 4.8-1 , both have this problem. thanks

Verilog hang jdk 16 or 17

one more hint, i got two computers, same jdk 16.0.1 and maven 3.8.3, one has 32GB ram and the other has 128GB ram. 128GB one works.

Verilog hang jdk 16 or 17

I trim down the target file so it complete in 48 sec (still very slow), below are the profile result, hope this help ``` ParseInfo parseInfo = parser.getParseInfo(); ATN atn...

Verilog hang jdk 16 or 17

@kaby76 thanks for your great answer, do you mind to post your fixed verilog2001.g4 please?

Verilog hang jdk 16 or 17

just followed your suggest, and i can make it 2s too, thank you very very much. Below is what i have changed. ``` conditional_statement : 'if' '(' expression ')' statement_or_null...

System.out.print(">") not work

this is a stupid fix, but at least it works ![image](https://user-images.githubusercontent.com/50471577/87225493-0435e700-c3c0-11ea-85f4-341e176a65e3.png)

System.out.print(">") not work

@YoungFrog really sad

how to escape the double quote of the command we send to capture command

i am sending the command via tcl port, not telnet. Some command need to use "capture", such as capture "ocd_reg" If pass the tcl statment to capture, such as echo...