Carlos Alberto Ruiz Naranjo comments

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                                            Carlos Alberto Ruiz Naranjo

project file order breaks project if not sorted like hierarchy using

I will fix it in the following days and I will send you a beta version to check it.

project file order breaks project if not sorted like hierarchy using

Could you send me an email to [email protected] ?

verible-verilog-format not works

I will take a look.

leaving state in fsm if begin end not used in verilog

I'm not Verilog user, but I think that it isn't possible to have a "case" with multiple statement and no "begin"-"end"

comment of 1st process after "begin" not recognized for documentation

Thanks for the report!

VHDL-LS linter process "vhdl_ls" remains active when closing VSCodium

Thanks, I can reproduce it.

[bug] Issues with file explorer opening location on Windows

I'm not sure what is the best option, it isn't a bug. What happen if you have 4 folders? What workspace folder should TerosHDL choose? It could be an option:

FuseSoC Support [Enhancement Draft]

It would be really nice. First I need to play with FuseSoC, so I can imagine how to do the graphical interface.

FuseSoC Support [Enhancement Draft]

@olofk could be possible to transform from .core project to array of EDAM projects, or will we lost any functionality? Maybe the generators? (I need to play with them)

FuseSoC Support [Enhancement Draft]

I certainly haven't thought of all the aspects... :sweat_smile: :sweat_smile: I'm trying to imagine how integrate FuseSoC in TerosHDL. For blinky example (https://github.com/fusesoc/blinky/blob/master/blinky.core) TerosHDL could create one FuseSoC project. The...