Carlos Alberto Ruiz Naranjo comments

Results 353 comments of


                                            Carlos Alberto Ruiz Naranjo

fsm isnt recognized - begin end bug

Can you provide a correct code example?

fsm isnt recognized - begin end bug

With no syntax errors.

Don't work Go To Definition with Verilog and SystemVerilog

Does it work fine the "outline"?

Don't work Go To Definition with Verilog and SystemVerilog

Ok, I see the problem. I will fix it.

An error occurred when writing Korean comments

Sorry @jeremiah-c-leary I forgot your comment. I'm refactoring TerosHDL. I will add tests for the VSG interface.

Integration with current VHDL VSCode extensions

I have added full support for VSG in TerosHDL: https://terostechnology.github.io/terosHDLdoc/style/start.html#vsg-vhdl-style-guide Formatter, linting, quick fixes...

Integration with current VHDL VSCode extensions

I have suggestions for a better integration. By I can open other issue.

Extension host crashes on `unhandledRejection`

Would be possible to use the verilog WASM for Linux? Or is there problems as in Windows?

"PermissionError: [WinError 5] Access is denied" when trying to run the test

I think it is a error in the installation of vunit. Can you create a run.py file and later?: ``` python run.py ``` What is the output?

"PermissionError: [WinError 5] Access is denied" when trying to run the test

I can't reproduce the error. 1. Can you check the permissions of the folder? C:\Users\admin\AppData\Local\Programs\Python\Python37-32\l 2. Can you install teroshdl backend and vunit with other python version?