Carlos Alberto Ruiz Naranjo
Carlos Alberto Ruiz Naranjo
Ok, I will take a look when I have time. El vie, 21 mar 2025, 23:29, Jakub Franek ***@***.***> escribió: > Hi @qarlosalberto , > > as expected it has...
Currently `ifdef` isn't supported.
Sadly it's not possible. TerosHDL recognizes VHDL and Verilog/SV independently.
Not in the near future, it's s big task.
Yes, I'm agree. Can you create an issue for that?
> Also, when opening vs code in a workspace directory, the corresponding project may be loaded. Don't know how easy this is to trigger. hmmm but you need to have...
Close as not planned.
1. Install this version: https://github.com/TerosTechnology/vscode-terosHDL/releases/tag/latest 2. Open a file, and save it. 3. Go to OUTPUT->TerosHDL:Debug and copy paste the text. Also share a screenshot. It will be similar to:...
Make sure that you aren't using a file with whitespaces in the path. And that your code is synthesizable. For example your testbench will fail because the code is'nt synthesizable.
@erik-ski are you using Project Schematic or File Schematic? Keep in mind that you need to use Project Schematic if you want to get the schematic for a project.