vscode-terosHDL
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Wrong port direction in Module documentation when `ifdef
Describe the bug When `ifdef is in port list, Module documentation has empty direction field for the next signal and that signal is not showing in the diagram.
Code
module test_module (
input wire port_name_01,
`ifdef M_01
output wire port_name_02,
inout wire port_name_03,
`endif
`ifdef M_02
input wire port_name_04,
output wire port_name_05,
inout wire port_name_06,
`endif
input wire port_name_07
);
endmodule
Please note that the issue affects only ports right after `ifdef: port_name_02 and port_name_04.
- OS: Win11 + RemoteSSH to Linux
- VSCode 1.88.1
Best regards, Daniel